The invention relates to a circuit and method for increasing the speed of performing an analog-to-digital conversion and more specifically to a circuit technique for avoiding the need to wait an excessively long time to allow settling of transients produced in a reference circuit due to large switching currents produced during a successive approximation procedure. The invention also relates to reducing RFI (radio frequency interference) problems caused by large, fast switching currents in a CDAC array during a successive approximation procedure.
In analog-to-digital converters which include CDACs (capacitive digital-to-analog converters), an analog input voltage is "sampled" onto a sampling capacitor. The sampled charge then is redistributed along with charge stored in binarily weighted bit capacitors which have previously been "updated" in accordance with digital feedback one bit at a time from the output of a comparator which "tests" the voltage of a charge summing conductor on which the charge redistribution occurs in accordance with a well known successive approximation procedure. The feedback bits are stored, one at a time starting with the MSB, in a SAR (successive approximation register). The charges of the binarily weighted bit capacitors and the input sampling capacitor are redistributed one bit at a time by successively connecting one terminal of each bit capacitor either to a precision reference voltage or to ground, according to whether a corresponding digital feedback bit is a "1" or a "0".
FIG. 1 shows a prior art reference voltage buffer circuit 13 connected to supply a precise reference voltage V.sub.REFOUT to the CDAC array 17. Reference voltage buffer circuit 13 includes an operational amplifier 13A and a unity gain buffer or amplifier circuit 13B. A precision input reference voltage V.sub.REFIN is applied by conductor 21 to the non-inverting input of operational amplifier 13A, the output 11 of which is applied to an input of unity gain buffer 13B. The output of unity gain buffer 13B provides the output reference voltage V.sub.REFOUT on conductor 14. Conductor 14 also is connected to the inverting input of operational amplifier 13A. Impedance 24 includes the internal resistance of unity gain buffer 13B, through which the current I.sub.REF flows. Conductor 14 is coupled by a metal-oxide-semiconductor field effect transistor (MOSFET) 26 to conductor 15, which is connected to CDAC capacitor array 17.
For simplification, the circuit in FIG. 1 shows the entire CDAC array as a single capacitor 17 having any of 2.sup.N values of a "code-dependant" capacitance C.sub.CDACi, where i is 1,2 . . . N, and N is the number of bits of the CDAC. During one successive approximation conversion of an analog input to an N-bit digital output, the "lumped" capacitor 17 will have N of the 2.sup.N possible values of C.sub.CDACi. (C.sub.CDACi can be thought of as being equal to the combined series capacitance of capacitors 17A and 17B in FIG. 3, as subsequently explained.) Digital feedback signals from a SAR (successive approximation register) produce the "equivalent" signals represented herein as Di and Di' to control switching of the individual bit capacitors which make up C.sub.CDACi. For simplification, the single MOSFET 26 is shown to represent the entire group of MOSFETs which selectively (in response to successive approximation feedback signals) couple one plate of each capacitor, respectively, of CDAC capacitor array 17 to reference voltage conductor 14. CDAC capacitor array 17 is shown as being also connected by MOSFET 29 to a ground conductor 33. Similarly, for simplification, the single MOSFET 29 is shown to represent the entire group of MOSFETs which selectively couple another plate of each capacitor of CDAC capacitor array 17, respectively, to the ground conductor 33.
MOSFETs 26 and 29 are turned on by the signals D.sub.i and D.sub.i ' when bit i of the CDAC capacitor array is switched to update bit i of the CDAC capacitor array. As subsequently explained with reference to FIGS. 3 and 3A, one skilled in the art will understand that switching of the capacitance of the CDAC array 17 can be modeled as charging of the above described code-dependent capacitance from a code-dependent initial voltage to the reference voltage. The signals D.sub.i and D.sub.i ' represent the successive approximation feedback signals to a bit capacitor of the CDAC array that is being switched in accordance with the successive approximation feedback. Note that D.sub.i logically ANDed with .phi..sub.2 to provide the gate control signal of MOSFET 26 and D.sub.i ' logically ANDed with .phi..sub.1 to provide the gate control signal for MOSFET 29 for simplicity are disclosed as individual logical signals; actually, D.sub.i and D.sub.i ' represent combinations of different successive approximation feedback logic levels applied to control the various bit capacitor MOSFET switches. Referring also to FIG. 2, the CDAC array capacitances C.sub.CDACi and the MOSFETs 19, 26, 29 and 37 for similarly are shown to represent combinations of switches coupled to the various individual CDAC bit capacitors. D.sub.i and D.sub.i ' are in phase, which is what is important to the explanation herein. That always results in I.sub.REF flowing from conductor 14 to ground conductor 33 or -V.sub.S as charge is redistributed in the CDAC capacitor array according to the successive approximation feedback from the comparator of the analog-to-digital converter.
The timing diagram of FIG. 1A shows the signal D.sub.i, which causes a current spike A in the current I.sub.REF to flow through the internal impedance 24 of unity gain amplifier 13B. The resulting voltage drop across internal impedance 24 produces a negative-going spike 35 in the voltage V.sub.REFOUT produced on conductor 14, and also causes oscillation or instability of V.sub.REFOUT during the interval 36.
Obviously, to achieve precise charge redistribution in the CDAC array, and hence an accurate successive approximation test of bit i of the CDAC, the oscillation during interval 36 must be allowed to settle before the next bit can be "updated" and tested because if V.sub.REFOUT oscillates, the voltage on conductor 16 likewise oscillates.
In a prior art product marketed by the present assignee, the ADS7805 analog-to-digital converter, the length of an interval similar to interval 36 in FIG. 1 (which must be long enough for the oscillation to settle) is the major factor in limiting the analog-to-digital conversion rate to approximately 100 kilohertz. In general, the length of the required settling time for precision reference voltage sources in analog-to-digital converters with internal CDACs has been a major factor limiting their analog-to-digital conversion speeds. Furthermore, as such analog-to-digital converters have been designed for shorter and shorter conversion times, the charging currents produced during updating of the internal CDACs have increased. This has resulted in increased RFI (radio frequency interference), in some cases to undesirably high levels.